Redirector Implementation
Hardware acceleration at each port for parsing packets at line-rate and performing sophisticated transformations
Distributed processing at each port for flexibility to add new redirection rules with no performance impact
- ASIC integrates two 100 MIPS RISC processors, and 10/100/1000 Ethernet MAC per port
Support for traditional L2 and L3 switching at wire-speed
Separate processors for background management functions
Multi-Gigabit switch backplane