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NANOG Meeting Presentation Abstract

Research Forum: 10 Gbps Line Speed Programmable Hardware for Open Source Network Processing Applications
Meeting: NANOG31
Date / Time: 2004-05-24 4:00pm - 5:00pm
Room: Grand Ballroom
Presenters: Speakers:
Livio Ricciulli, Metanetworks.
Abstract: We present the latest results of our NSF-sponsored research project to extend our existing 1-Gbps PCI-based traffic processing hardware to 10 Gbps.

The PCI card has two Ethernet ports and acts as a line speed Ethernet bridge with sub-microsecond latency. The card can be programmed with a large number of predefined stateful signatures that identify which packets are to be captured and/or blocked at line speed. Blocking/monitoring rules (specified as either Snort 2.x rules or BPF expressions) can be uploaded/modified in real-time by the host through the PCI without interrupting the packet flow.

The hardware has been designed to easily integrate with existing open source monitoring software. Using our approach, all existing sniffing applications, such as tcpdump, Snort, etc., can transparently benefit from the hardware line-speed acceleration without modification (as they see our hardware as a standard NIC in promiscuous mode).

Preliminary data indicates that a 10 Gbps version of our PCI traffic processing hardware (to be built later this year) is feasible at a surprisingly low cost. With our innovative design, the use of a XILINX virtexII-Pro FPGA and existing off-the-shelf components allows processing of approximately 625 Snort-like signatures at 10 Gbps line-speed with sub-microsecond latency. The increase in the number of rules scales linearly with the addition of FPGAs; thus, a 2-FPGA board would hold approximately 2*625 (1250) signatures, etc..

The programmable nature of this hardware technology can easily be adapted, modified and enhanced to accommodate new user-defined functions. An open-source hardware library of line-speed functions (common to both 1 Gbps and 10 Gbps) that go beyond the current capability is currently being worked on by a small research group. We hope to stimulate an exchange of ideas on the subject with the NANOG community. In particular, we hope to find out how to facilitate the adoption of this powerful new concept in an open-source, operational environment.
Files: pdfLivio Ricciulli Presentation(PDF)
youtubeResearch Forum: 10 Gbps Line Speed Programmable Hardware for Open Source Network Processing Applications
Sponsors: None.

Back to NANOG31 agenda.

NANOG31 Abstracts

  • Happy Packets - Initial Results
    Speakers:
    Randy Bush, IIJ; Tim GriffinIntel Research; .
    Zhuoqing MaoUniversity of Michigan; .
    Eric PurpusUniversity of Oregon; .
    Dan StutzbachUniversity of Oregon; .
  • Happy Packets - Initial Results
    Speakers:
    Randy Bush, IIJ; Tim GriffinIntel Research; .
    Zhuoqing MaoUniversity of Michigan; .
    Eric PurpusUniversity of Oregon; .
    Dan StutzbachUniversity of Oregon; .
  • Happy Packets - Initial Results
    Speakers:
    Randy Bush, IIJ; Tim GriffinIntel Research; .
    Zhuoqing MaoUniversity of Michigan; .
    Eric PurpusUniversity of Oregon; .
    Dan StutzbachUniversity of Oregon; .
  • Happy Packets - Initial Results
    Speakers:
    Randy Bush, IIJ; Tim GriffinIntel Research; .
    Zhuoqing MaoUniversity of Michigan; .
    Eric PurpusUniversity of Oregon; .
    Dan StutzbachUniversity of Oregon; .
  • Happy Packets - Initial Results
    Speakers:
    Randy Bush, IIJ; Tim GriffinIntel Research; .
    Zhuoqing MaoUniversity of Michigan; .
    Eric PurpusUniversity of Oregon; .
    Dan StutzbachUniversity of Oregon; .

 

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